This application relates to evaluation of curvatures and associated properties of line features formed on substrates.
Substrates formed of semiconductors, glasses or other suitable solid-state materials may be used as platforms to support various microstructures integrated to the substrates and to construct a wide range of substrate-based integrated devices. Examples of such substrate-based integrated devices include, among others, integrated electronic circuits, integrated optical devices, micro-electro-mechanical systems, flat panel display systems, or a combination of two or more of the above devices. Typically, various features are formed on a substrate to form a device. One mostly-used feature in substrate-based devices is a line feature which essentially is an elongated feature with one dimension, e.g., length, much greater than the other two dimensions, e.g., width and thickness.
Measurements of changes in stresses and deformation of a substrate and features fabricated on the substrate may have important applications. Different materials and different structures are usually formed on the same substrate and are in contact with one another. Some devices may also use complex multilayer geometry. Hence, the interfacing of different materials and different structures may cause a complex stress state in each feature due to differences in the material properties and the structure at interconnections under different fabrication condition and environmental factors (e.g., variations or fluctuations in temperature). In fabrication of an integrated circuit, for example, the stress state of the interconnect conducting lines may be affected by film deposition, rapid thermal cycling, chemical-mechanical polishing, and passivation during the fabrication process.
It is desirable to measure stresses on various features formed on the substrate to improve the design of the device structure, selection of materials, fabrication process, and other aspects of the devices so that the performance and reliability of the device can be enhanced. The stress measurements may be used to assess or evaluate the reliability of materials against failure from such phenomena as electromigration, stress-voiding and hillock formation. The stress measurements may also be used to facilitate quality control of the mechanical integrity and electromechanical functioning of circuit chip dies during large scale production in wafer fabrication facilities. In addition, the stress measurements may be used to improve the design of various thermal treatments (such as temperature excursions during passivation) and chemical and mechanical treatments (such as polishing) to reduce their contribution to the residual stresses in the final device.
The present disclosure includes analytical methods to compute curvatures of line features embedded in a medium formed over a substrate based on thermoelastic properties of the structures. Such embedded line features on substrates are used in various substrate-based components and devices. One example is conducting lines (e.g., metal lines) imbedded in an insulator layer (e.g., an oxide or nitride layer) over a semiconductor or other substrate. Curvatures of embedded line features with and without an overlying passivation layer may be calculated. Applications of such analytical methods are also disclosed.